Provision of a built-in, self-test capability within an integrated circuit enables faults or other problems that might arise in the operation of the circuit to be identified much more rapidly than might occur as the result of periodically scheduled, externally applied tests. Immediate identification of such faults can be extremely important in certain applications, especially those involving human safety. For example, failure of integrated circuits used in aviation systems may pose a significant risk to the lives of all the passengers on an aircraft. To minimize the impact of such failures, multiple redundant integrated circuits are often used, particularly in critical components. Early detection of a problem, even in a multiple redundant system, can provide an improved safety margin by permitting corrective action to be taken as soon as possible. For example, once a failed component is detected in a critical system, the system can reconfigure itself to use other redundant components, locking out the failed component.
A fault in certain types of integrated circuits might not readily be detected until a test of all possible operating states of the circuit revealed the problem, since the input data normally processed by the circuit may have a relatively limited range. Accordingly, any self test that relies upon normal input data to evaluate an integrated circuit's operation may fail to properly detect a problem. External test circuitry used to generate a full range of operating states that are required to completely test an integrated circuit can add significant cost and operating overhead to a system, particularly where normal use of an integrated circuit is interrupted to implement its test. A self test can be initiated each time a circuit is energized, at periodic timed intervals during its use, or on demand; however, a conventional self test usually interrupts the normal operation and function of the circuit under test. This interruption typically continues until the test is fully completed. However, for critical systems in which each component should be fully tested from time to time during continued operation of the system, it may not be possible to interrupt the normal operation to carry out a test of specific key components.
For example, a multiple redundant central processing unit and memory system on an aircraft or in other critical applications may use a plurality of error detection and correction (EDAC) circuits connected between the multiple central processing units and memory circuits to insure that data written to memory are accurately stored and read back from memory. It would be impractical to externally periodically apply a test signal to the EDACs to test for a fault, since they would have to be rendered inoperative during such a test. Providing an external test signal generator for each EDAC would also be prohibitively expensive. Yet, fault-free operation of each EDAC in the redundant system is critical to the system's overall reliability. One solution to this problem is to use a technique called "cycle stealing" that is described in commonly assigned U.S. Pat. No. 5,144,230. This technique allows a self test to be run concurrently with the normal operation of the circuit under test. At least a portion of the self test is completed during each clock cycle while the circuit is not being used for its normal function. The technique thus allows a full test of a circuit to be completed over a number of clock cycles without any interruption of the normal functions provided by the circuit.
Self test using cycle stealing solves part of the problem. However, it may not be economical to provide a full test generator on each integrated circuit being tested, e.g., on each EDAC. One test generator can simultaneously test several EDACs, but although use of a single test generator to provide the test signal for a plurality of such devices helps to defray the cost, it does not represent a complete solution to the problem. The self-test system should be low in cost and fully integrated into the circuit comprising the devices to be tested.
Accordingly, an object of this invention is to provide an economical built-in self-test system for testing an integrated circuit. It is a further object to provide a built-in self-test system for testing a plurality of common sub-circuits comprising the integrated circuit. Yet a further object is to provide a self-test system that minimizes the cost of a test generator used to generate test signals capable of substantially fully testing the integrated circuit. A still further object is to provide a self-test system and method that is usable to test an EDAC. These and other advantages and objects of the invention will be apparent from the attached drawings and the Description of the Preferred Embodiments that follows.